SystemVerilog Introduction

  • SystemVerilog is an extension of Verilog with many verification features that allow engineers to verify the complex design using randomized testbench.
  • SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.
  • SystemVerilog was created by the donation of the Superlog language to Accellera in 2002.
  • The most of the verification functionality is based on the OpenVera language donated by Synopsys.The donations included testbench constructs based on Vera, OpenVera assertions, Synopsys’ VCS DirectC simulation interface to C and C++, and a coverage application programming interface that provides links to coverage metrics.
  • In 2005, SystemVerilog was adopted as IEEE Standard 1800-2005 . In 2009, the standard was merged with the base Verilog (IEEE 1364-2005) standard, creating IEEE Standard 1800-2009.The current version is the IEEE standard 1800-2017.